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fedd51v18160f-03 1 semiconductor this version: may 2001 previous version : jan. 2000 msm51v18160f 1,048,576-word 16-bit dynamic ram : fast page mode type 1/15 description the msm51v18160f is a 1,048,576-word 16-bit dynamic ram fabricated in oki?s silicon-gate cmos technology. the msm51v18160f achieves high integration, high-speed operation, and low- power consumption because oki manufactures the device in a quadruple-layer polysilicon/double-layer metal cmos process. the msm51v18160f is available in a 42-pin plastic soj or 50/44-pin plastic tsop. features ? 1,048,576-word 16-bit configuration ? single 3.3v power supply, 0.3v tolerance ? input : lvttl compatible, low input capacitance ? output : lvttl compatible, 3-state ? refresh : 1024 cycles/16ms ? fast page mode, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? packages 42-pin 400mil plastic soj ( soj42-p-400-1.27 ) (product : msm51v18160f-xxjs) 50/44-pin 400mil plastic tsop ( tsopii50/44-p-400-0.80-k ) (product : msm51v18160f-xxts-k) xx indicates speed rank. product family access time (max.) power dissipation family t rac t aa t cac t oea cycle time (min.) operating (max.) standby (max.) 50ns 25ns 13ns 13ns 90ns 450mw 60ns 30ns 15ns 15ns 110ns 414mw msm51v18160f 70ns 35ns 20ns 20ns 130ns 378mw 1.8mw
fedd51v18160f-03 1 semiconductor msm51v18160f 2/15 pin configuration (top view) pin name function a0?a9 address input ras row address strobe lcas lower byte column address strobe ucas upper byte column address strobe dq1?dq16 data input/data output oe output enable we write enable v cc power supply (3.3v) v ss ground (0v) nc no connection note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. 42-pin plastic soj 50/44-pin plastic tsop (k type) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 dq1 dq2 dq3 dq4 v cc v cc v cc v ss v ss v ss dq16 dq15 dq14 dq13 dq12 dq11 dq10 dq9 a 9 a 8 a 7 a 6 a0 a1 a2 a3 dq5 dq6 dq7 dq8 nc nc we r a s nc nc nc a 5 a 4 l cas u cas o e 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 dq1 dq2 dq3 dq4 v cc v cc a3 v ss v ss v ss dq16 dq15 dq14 dq13 dq12 dq11 dq10 dq9 a 9 a 8 a 7 a 6 nc a0 a1 a2 dq5 dq6 dq7 dq8 nc nc nc w e ra s nc nc a 5 a 4 l cas u ca s o e 22 23 24 25 29 28 27 26 v cc nc
fedd51v18160f-03 1 semiconductor msm51v18160f 3/15 block diagram function table input pin dq pin ras lcas ucas we oe dq1-dq8 dq9-dq16 function mode h * * * * high-z high-z standby l h h * * high-z high-z refresh llhhl d out high-z lower byte read lhlhl high-z d out upper byte read lllhl d out d out word read llhlh d in don?t care lower byte write l h l l h don?t care d in upper byte write llllh d in d in word write l l l h h high-z high-z ? * : ?h? or ?l? a0 - a9 8 8 8 8 8 8 8 16 8 16 10 10 10 10 timing generator column address buffers i/o controller internal address counter row address buffers refresh control clock i/o controller column decoders sense amplifiers memory cells word drivers row deco- ders i/o selector input buffers input buffers output buffers output buffers dq1-dq8 dq9-dq16 oe we ras lcas ucas v cc v ss on chip v bb generator on chip iv cc generator
fedd51v18160f-03 1 semiconductor msm51v18160f 4/15 electrical characteristics absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out ?0.5 to v cc + 0.5 v voltage v cc supply relative to v ss v cc ?0.5 to 4.6 v short circuit output current i os 50 ma power dissipation p d* 1w operating temperature t opr 0 to 70 c storage temperature t stg ?55 to 150 c *: ta = 25 c recommended operatiing conditions (ta = 0 to 70c) parameter symbol min. typ. max. unit v cc 3.0 3.3 3.6 v power supply voltage v ss 000v input high voltage v ih 2.0 ? v cc + 0.3 *1 v input low voltage v il ? 0.3 *2 ? 0.8 v notes: *1. the input voltage is v cc + 1.0v when the pulse width is less than 20ns (the pulse width is with respect to the point at which v cc is applied). *2. the input voltage is v ss ? 1.0v when the pulse width is less than 20ns (the pulse width respect to the point at which v ss is applied). pin capacitance (vcc = 3.3v 0.3v, ta = 25c, f = 1 mhz) parameter symbol min. max. unit input capacitance (a0 - a9) c in1 ?5pf input capacitance ( ras , lcas , ucas , we , oe ) c in2 ?7pf output capacitance (dq1 - dq16) c i/o ?7pf
fedd51v18160f-03 1 semiconductor msm51v18160f 5/15 dc characteristics (v cc = 3.3v 0.3v, ta = 0 to 70c) msm51v18160 f-50 msm51v18160 f-60 msm51v18160 f-70 parameter symbol condition min. max. min. max. min. max. unit note output high voltage v oh i oh = ? 2.0ma 2.4 v cc 2.4 v cc 2.4 v cc v output low voltage v ol i ol = 2.0ma 0 0.4 0 0.4 0 0.4 v input leakage current i li 0v v i v cc + 0.3v; all other pins not under test = 0v ? 10 10 ? 10 10 ? 10 10 a output leakage current i lo dq disable 0v v o v cc ? 10 10 ? 10 10 ? 10 10 a average power supply current (operating) i cc1 ras , cas cycling, t rc = min. ? 125 ? 115 ? 105 ma 1,2 ras , cas = v ih ? 2 ? 2 ? 2 power supply current (standby) i cc2 ras , cas v cc ? 0.2v ? 0.5 ? 0.5 ? 0.5 ma 1 average power supply current ( ras -only refresh) i cc3 ras cycling, cas = v ih , t rc = min. ? 125 ? 115 ? 105 ma 1,2 power supply current (standby) i cc5 ras = v ih , cas = v il , dq = enable ? 5 ? 5 ? 5ma1 average power supply current ( cas before ras refresh) i cc6 ras = cycling, cas before ras ? 125 ? 115 ? 105 ma 1,2 average power supply current (fast page mode) i cc7 ras = v il , cas cycling, t pc = min. ? 85 ? 80 ? 75 ma 1,3 notes: 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih .
fedd51v18160f-03 1 semiconductor msm51v18160f 6/15 ac characteristics (1/2) (v cc = 3.3v 0.3v, ta = 0 to 70c) note1,2,3 msm51v18160 f-50 msm51v18160 f-60 msm51v18160 f-70 parameter symbol min. max. min. max. min. max. unit note random read or write cycle time t rc 90 ? 110 ? 130 ? ns read modify write cycle time t rwc 131 ? 155 ? 185 ? ns fast page mode cycle time t pc 35 ? 40 ? 45 ? ns fast page mode read modify write cycle time t prwc 76 ? 85 ? 100 ? ns access time from ras t rac ? 50 ? 60 ? 70 ns 4, 5, 6 access time from cas t cac ? 13 ? 15 ? 20 ns 4, 5 access time from column address t aa ? 25 ? 30 ? 35 ns 4, 6 access time from cas precharge t cpa ? 30 ? 35 ? 40 ns 4, 12 access time from oe t oea ? 13 ? 15 ? 20 ns 4 output low impedance time from cas t clz 0 ? 0 ? 0 ? ns 4 cas to data output buffer turn- off delay time t off 013015020ns7 oe to data output buffer turn-off delay time t oez 013015020ns7 transition time t t 150150150ns3 refresh period t ref ? 16 ? 16 ? 16 ms ras precharge time t rp 30 ? 40 ? 50 ? ns ras pulse width t ras 50 10,000 60 10,000 70 10,000 ns ras pulse width (fast page mode) t rasp 50 100,000 60 100,000 70 100,000 ns ras hold time t rsh 13 ? 15 ? 20 ? ns ras hold time referenced to oe t roh 13 ? 15 ? 20 ? ns cas precharge time (fast page mode) t cp 7 ? 10 ? 10 ? ns 14 cas pulse width t cas 13 10,000 15 10,000 20 10,000 ns cas hold time t csh 50 ? 60 ? 70 ? ns cas to ras precharge time t crp 5 ? 5 ? 5 ? ns 12 ras hold time from cas precharge t rhcp 30 ? 35 ? 40 ? ns 12 ras to cas delay time t rcd 17 37 20 45 20 50 ns 5 ras to column address delay time t rad 12 25 15 30 15 35 ns 6 row address set-up time t asr 0 ? 0 ? 0 ? ns
fedd51v18160f-03 1 semiconductor msm51v18160f 7/15 ac characteristics (2/2) (v cc = 3.3v 0.3v, ta = 0 to 70c) note1,2,3 msm51v18160 f-50 msm51v18160 f-60 msm51v18160 f-70 parameter symbol min. max. min. max. min. max. unit note row address hold time t rah 7 ? 10 ? 10 ? ns column address set-up time t asc 0 ? 0 ? 0 ? ns 11 column address hold time t cah 7 ? 10 ? 15 ? ns 11 column address to ras lead time t ral 25 ? 30 ? 35 ? ns read command set-up time t rcs 0 ? 0 ? 0 ? ns 11 read command hold time t rch 0 ? 0 ? 0 ? ns 8, 11 read command hold time referenced to ras t rrh 0 ? 0 ? 0 ? ns 8 write command set-up time t wcs 0 ? 0 ? 0 ? ns 9, 11 write command hold time t wch 7 ? 10 ? 15 ? ns 11 write command pulse width t wp 7 ? 10 ? 10 ? ns oe command hold time t oeh 13 ? 15 ? 20 ? ns write command to ras lead time t rwl 13 ? 15 ? 20 ? ns write command to cas lead time t cwl 13 ? 15 ? 20 ? ns 13 data-in set-up time t ds 0 ? 0 ? 0 ? ns 10, 11 data-in hold time t dh 7 ? 10 ? 15 ? ns 10, 11 oe to data-in delay time t oed 13 ? 15 ? 20 ? ns cas to we delay time t cwd 36 ? 40 ? 50 ? ns 9 column address to we delay time t awd 48 ? 55 ? 65 ? ns 9 ras to we delay time t rwd 73 ? 85 ? 100 ? ns 9 cas precharge we delay time t cpwd 53 ? 60 ? 70 ? ns 9 cas active delay time from ras precharge t rpc 5 ? 5 ? 5 ? ns 11 ras to cas set-up time ( cas before ras ) t csr 5 ? 5 ? 5 ? ns 11 ras to cas hold time ( cas before ras ) t chr 10 ? 10 ? 10 ? ns 12
fedd51v18160f-03 1 semiconductor msm51v18160f 8/15 notes: 1. a start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. -50 is measured with a load circuit equivalent to 1 ttl load and 50pf, and -60/-70 is measured with a load circuit equivalent to 1 ttl load and 100pf. the output timing reference levels are v oh =2.0 and v ol =0.8v. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) and t oez (max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle. 9. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd t cwd (min.), t rwd t rwd (min.), t awd t awd (min.) and t cpwd t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. these parameters are referenced to the ucas and lcas , leading edges in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle. 11. these parameters are determined by the falling edge of either ucas or lcas , whichever is earlier. 12. these parameters are determined by the rising edge of either ucas or lcas , whichever is later. 13. t cwl should be satisfied by both ucas and lcas . 14. t cp is determined by the time both ucas and lcas are high.
fedd51v18160f-03 1 semiconductor msm51v18160f 9/15 timing chart read cycle write cycle (early write) t off t clz t cac t oea t asc t rrh t rah t asr t rad t ral t crp t cah t crp t rcd t rc t ras t rp t csh t rsh t cas t rac t aa t rcs t roh t rch t oez row column valid data-out o p en ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v oh v ol ?h? or ?l? t crp t rp t rwl valid data-in t dh t ds t wcs t wch t cwl t asr t rah t asc t rc t ras row t csh t crp t rcd t rsh t cas column t cah t rad t ral t wp ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v ih v il ?h? or ?l? open
fedd51v18160f-03 1 semiconductor msm51v18160f 10/15 read modify write cycle t rsh t cas t rwc t cwl t rwl t crp t rp t oed t cwd t awd t oeh t wp t oez t cac t dh t ds valid data-out valid data-in t aa t rwd row colum t rac t oea t rcs t cah t asc t asr t rah t rad t crp t rcd t csh t ras t clz ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v i/oh v i/ol ?h? or ?l?
fedd51v18160f-03 1 semiconductor msm51v18160f 11/15 fast page mode read cycle fast page mode write cycle (early write) t clz t oea t rcs t oez t cac t rrh t rch t rcs t cpa t rch t aa t oea t off t oez t clz t off t cah t cas t ral t asc t rsh t cp t cah t rp t rhcp column t crp t pc t off t cac t csh t cac t oez t rac t oea t rch t cpa t aa t aa t cah t asc t rah t rad t rcs t asr t asc t cp t cas t rasp t cas t rcd t crp t clz valid data-out row column column ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v oh v ol ?h? or ?l? valid data-out valid data-out t wp t cwl t wch t asc t cp t pc t rasp column t ral t crp t asc t cah t cah t cas t rsh t cp t cas t rp t rhpc column t wp t wch t dh t ds t dh t ds valid * data-in t wcs t wcs valid * data-in t cwl t csh t rad t asr t asc t rah t rcd t crp t cas t cah row column t wp t rwl t wch t cwl t dh t ds t wcs valid * data-in ?h? or ?l? ra s v ih v il ca s v ih v il address v ih v il w e v ih v il dq v ih v il note: oe = ?h? or ?l?
fedd51v18160f-03 1 semiconductor msm51v18160f 12/15 fast page mode read modify write cycle ras ras ras ras -only refresh cycle t ds t aa t dh t roh t oea t wp t cpa t ds t oez t cpwd t wp t cwd t awd t dh t awd t aa t rac t rcs t rcs t aa t cpa t oea t pwd t cwd t asc t rah t asr t rad t csh t cas t rasp t cwl t rcd t cp t cah t asc row column t rwl t cwl t rcs column t cwl t cwd t ral t cah t crp t cp t cas t clz t cas t asc t oed t oez t oed t cac t oed t dh t oez in t wp t ds column t rp t rsh t cah out t cac t prwc t cac t clz t clz t awd t oea in in out out t cpwd ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v i/oh v i/ol ?h? or ?l? note: in = valid data-in, out = valid data-out t asr t rah t crp t rpc t rp t ras t rc t off row ras v ih v il ca s v ih v il v ih v il address v oh v ol dq ?h? or ?l? o p en note: we , oe = ?h? or ?l?
fedd51v18160f-03 1 semiconductor msm51v18160f 13/15 cas cas cas cas before ras ras ras ras refresh cycle hidden refresh read cycle ra s t off t rpc t rp t rc t ras t chr t csr t rp t cp t rpc v ih v il ca s v ih v il v oh v ol dq o p en note: we , oe , address = ?h? or ?l? ?h? or ?l? t cac t cah column t rsh t rrh t rp t ras t rp t chr t off t oez t rac t clz t roh t oea t aa t ral t rcs t rah t asr t asc t rad t ras t rcd t crp t rc row t rc ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v oh v ol o p en valid data-out ?h? or ?l?
fedd51v18160f-03 1 semiconductor msm51v18160f 14/15 hidden refresh write cycle t rp t ras t rc t rp t chr t ds t dh t wch t wp t wcs column row valid data-in t ral t cah t rah t asr t asc t rad t ras t rsh t rcd t crp t rc ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v ih v il ?h? or ?l?
fedd51v18160f-03 1 semiconductor msm51v18160f 15/15 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. c o p y r i g h t 200 1 o k i e l ec t r i c i n d u s t r y c o ., l t d.

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